The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for forming a contact hole for an electrode region or a groove for an element isolation region of an IC or LSI.
P-n junction isolation and selective oxidation have been used as methods for isolating semiconductor elements, especially in the manufacture of bipolar ICs and MOSICs.
However, the above methods have the following drawbacks. For example, in the p-n junction isolation method, lateral diffusion is so great that the packing density is lowered. In the selective oxidation method, an increase in stress due to lateral oxidation at the edge of a field oxide layer results in crystal defects. Lateral oxidation of the film degrades patterning, so that a high packing density cannot be achieved.
In consideration of the above drawbacks, the present inventors have previously proposed the following element isolation method. As shown in FIG. 1, a U-shaped groove 2 is formed in a semiconductor layer 1. The groove 2 has a depth D1, a width W1, and has vertical or substantially vertical walls. In this case, if the ratio of the depth D1 to the width W1 (D1/W1) is relatively small, the groove 2 is gradually filled by an insulating film 3, provided a thickness of the insulating film 3 is sufficiently greater than half the width W1 of the groove 2. As a result, the surface of the insulating film 3 becomes flat. Thereafter, the insulating film 3 is selectively etched to expose one major surface of the semiconductor layer 1 to form an insulating isolation region in the groove 2, although the etching process is not illustrated in FIG. 1. In this method, if the depth D1 is increased with respect to the width W1, a cavity 4 is formed in the insulating film 3 inside a groove 2'. This is because the deposition components of the insulating film are not always deposited vertically with respect to one major surface of the semiconductor layer. Some of the components are obliquely deposited in the groove 2' and cannot enter the deeper portion thereof. As a result, some of the components are deposited near the surface of the groove 2'.
A method has also been proposed for forming an element isolation region which comprises an insulator deposited in a Y-shaped groove.
Referring to FIG. 3A, an SiO.sub.2 film 22 of about 1,000.ANG. thickness and an Si.sub.3 N.sub.4 film 23 of about 3,000.ANG. thickness are sequentially deposited on a silicon semiconductor layer 21 with a (100) plane. The Si.sub.3 N.sub.4 film 23 is then selectively etched by photoetching to form a hole 24. The SiO.sub.2 film 22 is then overetched using the Si.sub.3 N.sub.4 film 23 as a mask, to form a hole 25 whose diameter is larger than that of the hole 24 (FIG. 3A).
The exposed part of the silicon semiconductor layer 21 is then etched by an anisotropic etchant of the KOH type with the SiO.sub.2 film 22 serving as a mask to form a first groove 26 having a tapered shape (FIG. 3B). Subsequently, that part of the silicon semiconductor layer 21 which corresponds to the first groove 26 is etched by anisotropic etching such as the reactive ion etching method to form a second groove 27 (FIG. 3C).
After the Si.sub.3 N.sub.4 film 23 and the SiO.sub.2 film 22 are removed, an isolation region formation film 28 such as an SiO.sub.2 film is deposited to fill the first and second grooves 26 and 27 and to cover the entire surface (FIG. 3D). The isolation region formation film 28 is then etched to expose the one major surface of the semiconductor layer 21 to leave isolating material 28' in the first and second grooves 26 and 27. Thus, an element isolation region 29 is formed (FIG. 3E).
According to the latter method, since the Y-shaped groove comprises the first and second grooves 26 and 27, the isolating film is properly formed to provide excellent step coverage. The cavity 4 shown in FIG. 2 may not be formed. However, the following drawbacks are presented:
(1) Since a width A of the first groove is determined by the width of the hole 25 when the exposed portion of the SiO.sub.2 film 22 is overetched using the Si.sub.3 N.sub.4 film 23 as the mask, the width A of the first groove 26 may change in accordance with the degree of etching. Hence, the width of the element isolation region 29 can hardly be controlled.
(2) Since the tapered portion of the first groove 26 of the semiconductor layer 21 as shown in FIG. 3B which will form the isolation region of the MOS semiconductor device is covered with the Si.sub.3 N.sub.4 film 23, it is difficult to ion-implant impurities for formation of a channel stopper in the tapered portion of the groove. In order to form such a channel stopper in the tapered portion, the second groove 27 must be formed in FIG. 3C. After the Si.sub.3 N.sub.4 film 23 is etched, ion-implantation is performed using the SiO.sub.2 film 22 with the hole 24 as the mask. Thus, the channel stopper is formed in the tapered portion. However, the channel stopper is also formed at the bottom of the groove; it is impossible to form the channel stopper only in the tapered portion.
When a contact hole of a diameter substantially the same as the thickness of the field film on the semiconductor layer is formed for connection of an electrode of the semiconductor device, the diameter of the hole is inadvertently increased if the conventional isotropic etching method and the tapered etching method are used. This is undesirable from the viewpoint of micropatterning. In order to solve the above problem, anisotropic etching such as reactive ion etching is used. However, this increases the depth of the hole with respect to its width; step coverage of the electrode material is degraded as described with reference to FIG. 2, thus forming a cavity therein.